Locked loop circuits, such as phase locked loop circuits, are basic components of radio, wireless, and telecommunication technologies. A phase locked loop or phase lock loop (PLL) is a control system that generates an output signal having a phase related to the phase of an input signal.
A sample PLL is now described with reference to FIG. 1. The PLL 50 includes a variable frequency oscillator 58 (here, a voltage controller oscillator VCO), a divider 60, a phase frequency detector (PFD) 52, a charge pump 54, and a loop filter 56. The VCO 58 generates a periodic signal Fout, and the divider 60 divides the frequency of the output signal Fout, to produce signal Fdiv. The phase frequency detector 52 compares the phase of that signal Fdiv with the phase of a reference periodic signal Fref, and generates the control signals UP, DN for the charge pump 54 based based that phase comparison. When the phase of the signal Fref leads the phase of the signal Fdiv, the control signal UP is asserted at a logic high, while the control signal DN remains at a logic low. Conversely, when the phase of the signal Fref lags the phase of the signal Fdiv, the control signal DN is asserted at a logic high, while the control signal UP remains at a logic low. When the phase of the signal Fref and the phase of the signal Fdiv match, neither UP nor DN are asserted logic high.
The charge pump 54 generates a control signal for the VCO 58, which is passed through the loop filter 56, which extracts the low frequency content of the control signal. The VCO 58, in response to the control signal, adjusts the phase and frequency of the output signal Fout. When UP is asserted, the charge pump 54 increases the voltage of the control signal, as opposed to decreasing the voltage of the control signal when DN is asserted. Those of skill in the art will appreciate that since the phase of the signal Fref cannot both lead and lag the phase of the signal Fdiv, the phase frequency detector 110 will not simultaneously assert both UP and DN.
In addition to synchronizing signals, the PLL 50 can track an input frequency, or it can generate a frequency that is a multiple (or fraction) of the input frequency.
Such phase locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to provide inputs to circuits that demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase locked loop building block, phase locked loops are widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.
In some cases, it may be desirable for a phase locked loop to be operable over a wide band of frequencies. In order to produce such wide band phase locked loops, a charge pump circuit is typically employed in the loop to generate the control signals sent to the oscillator.
As stated, in some cases, a PLL may generate a frequency that is a fraction of the input frequency. However, the bandwidth of such a PLL may be low, and the lock time may be undesirable high. In addition, the reduction of jitter in such designs is difficult.
Therefore, further development work on PLL circuits is needed.